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lt3587 1 3587fc typical application features applications description high voltage monolithic inverter and dual boost the lt ? 3587 provides a one chip solution for applications requiring two positive and one negative high voltage sup- plies. the lt3587 input voltage range of 2.5v to 6v makes it ideal for various battery-powered systems. a single resistor programs each of the three output voltage levels and the output current of boost3. the intelligent soft- start allows for sequential soft-start of the boost1 output followed by the negative output with a single capacitor. internal sequencing circuitry also disables the inverter until the boost1 output has reached 87% of its ? nal value. the lt3587 integrates all the power switches, soft-start, and output-disconnect circuits into a small 3mm 3mm qfn package. this high level of integration combined with small external components makes the lt3587 ideal for space constrained applications. l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. li-ion powered supply for ccd imager and six white backlight leds n ideal for ccd, lcd, led backlight and oled applications n easy generation of 15v (50ma), C8v (100ma) and 20v (20ma) from a li-ion cell n v vin range: 2.5v to 6v n wide output ranges: up to 32v for the boosts and up to C32v for the inverter n output disconnect for the boost channels n boost3 allows voltage programming and/or current programming for a one wire current source n overload fault protection with fault i/o pin indicator n combined soft-start and enable pins n small 20-pin 3mm 3mm qfn package n digital still and video cameras n scanner and display systems n pda, cellular phones and handheld computers n led backlight and oled display drivers n ccd imager bias n general high voltage supply bias ef? ciency curve 15 h 10 h 3587 ta01a v out3 cap3 v fb3 i fb3 sw2 fb2 gnd cap1 fb1 v out1 lt3587 flt en/ss1 en/ss3 sw3 sw1 v in 10 f v vin 2.5v to 6v 2.2 f 15 h1 5 h ccd positive 15v, 50ma ccd negative C8v, 100ma 8.06k 1 f led driver 20ma, up to 6 leds 2.2 f 1m1m 22 f v vin 2.5v to 6v 2.7 p f 6.8pf normalized current 0 efficiency (%) power dissipation (mw) 9085 75 65 55 8070 60 50 800700 500 300 100 600400 200 0 1 3587 ta01b 1.5 0.5 cdd + = 50ma cdd C = 100ma led = 20ma cdd + cdd C led all channels enabled power dissipation all channels enabled downloaded from: http:///
lt3587 2 3587fc absolute maximum ratings v in ..............................................................................6v soft-start input pins en/ss1, en/ss3 .....................................................6v feedback pins fb1, fb2, i fb3 , v fb3 ................................. C0.2v to 6v high voltage switch pins sw1, sw2, sw3 ...................................................40v high voltage output pins cap1, cap3, v out1 , v out3 ...................................32v bidirectional i/o pin flt ..........................................................................6v flt current ........................................................10ma operating junction temperature range .. C40c to 125c storage temperature range ................... C65c to 125c (note 1) 20 19 18 17 16 7 8 top view 21 ud package 20-lead (3mm s 3mm) plastic qfn 9 10 v out3 cap3 sw3 gnd flt fb1v out1 cap1gnd sw1 v fb3 i fb3 en/ss3v in en/ss1 fb2 gndgnd sw2 nc 12 11 13 14 15 4 5 3 2 1 6 ja = 68c/w, jc = 4.2c/w exposed pad (pin 21) is gnd, must be soldered to pcb parameter conditions min typ max units operating input voltage range 2.5 6 v quiescent current v en/ss1 = 0v, v en/ss3 = v vin or v en/ss1 = v vin , v en/ss3 = 0v or v en/ss1 = v en/ss3 = v vin not switching 2.4 4 ma v en/ss1 = v en/ss3 = 0v, in shutdown 5.5 9 a switching frequency l 0.8 1 1.2 mhz maximum duty cycle l 87 93 % minimum on time 50 70 ns power fault delay from any output to flt 16 ms flt input threshold low l 0.4 1.0 1.6 v flt leakage current v flt = 5v l 1 a flt voltage output low i flt = 1ma l 0.4 v order information lead free finish tape and reel part marking package description temperature range lt3587eud#pbf lt3587eud#trpbf ldnc 20-lead (3mm 3mm) plastic qfn C40c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ pin configuration electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v vin = 3.6v, v en/ss1 = v en/ss3 = v vin unless otherwise noted (note 2, 3). downloaded from: http:///
lt3587 3 3587fc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v vin = 3.6v, v en/ss1 = v en/ss3 = v vin unless otherwise noted (note 2, 3). parameter conditions min typ max units boost1 cap1 bias current v cap1 = 15v, v out1 = open 60 150 a fb1 reference voltage l 1.19 1.22 1.25 v v out1 output voltage r fb1 = 1m l 14.25 15 15.75 v sw1 current limit 800 990 ma sw1 v cesat i sw1 = 400ma 200 mv sw1 leakage current v sw1 = 15v 0.1 5 a en/ss1 for full inductor current v fb1 = 1.1v, v fb2 = 0.1v 2.5 v en/ss1 shutdown voltage threshold l 0.2 v en/ss1 pin bias current v en/ss1 = 0v C0.5 C1 C1.5 a v out1 current limit v cap1 = 15v 100 155 ma cap1 to v out1 on-resistance (r disc1 )v cap1 = 15v, i vout1 = 50ma 5 8 v out1 disconnect leakage v vin = v cap1 = 6v, v vout1 = 0v 0.1 1 a inverter fb2 reference voltage l C10 5 20 mv output voltage r fb2 = 1m l C7.5 C8 C8.5 v sw2 current limit 900 1090 ma sw2 v cesat i sw2 = 600ma 250 mv sw2 leakage current v sw2 = 15v 0.1 5 a fb1 threshold to start negative channel percent of final regulation value 87 90 % boost3 cap3 bias current v cap3 = 15v, v out3 = open 70 150 a boost3 programmed current r ifb3 = 8.06k l 18 20 22 ma v fb3 reference voltage r vfb3 = 1m, i vout3 = 20ma l 0.77 0.8 0.83 v v out3 output voltage r vfb3 = 1m, i vout3 = 20ma l 14 15 16 v sw3 current limit 400 480 ma sw3 v cesat i sw3 = 200ma 250 mv sw3 leakage current v sw3 = 15v 0.1 5 a en/ss3 for full inductor current v vfb3 = v ifb3 = 0.6v 2 v en/ss3 shutdown voltage threshold l 0.2 v en/ss3 pin bias current v en/ss3 = 0v C0.5 C1 C1.5 a v out3 current limit v cap3 = 15v, v ifb3 = 0v 70 110 ma cap3 to v out3 on resistance (r disc3 )v cap3 = 15v, i vout3 = 20ma 10 15 v out3 disconnect leakage v vin = v cap3 = 6v, v vout3 = 0v 0.1 1 a cap3 pin overvoltage clamp 27 29 31 v note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into pins are positive; all voltages are referenced to gnd unless otherwise noted. note 3: the lt3587 is guaranteed to meet speci? ed performance from 0c to 125c. speci? cations over the C40c to 125c operating range are assured by design, characterization and correlation with statistical process controls. downloaded from: http:///
lt3587 4 3587fc typical performance characteristics shutdown quiescent current vs input supply voltage quiescent current when on but not switching vs input supply voltage v in uvlo voltage vs temperature fb1, v fb3 and i fb3 regulation voltage vs temperature fb2 regulation voltage vs temperature fb1, v fb3 , i fb3 bias current in regulation vs temperature speci? cations are at t a = 25c unless otherwise noted. fb2 bias current in regulation vs temperature input voltage (v) 2.5 quiescent current (a) 10 86 4 2 4 3.5 5 3587 g01 6 5.5 3 4.5 125c 90c 25c C40c v vin = 3.6v en/ss1 = en/ss3 = 0v input voltage (v) 2.5 quiescent current (ma) 3.53.0 2.5 2.0 1.5 4 3.5 5 3587 g02 6 5.5 3 4.5 125c 90c 25c C40c v vin = en/ss1 = en/ss3 = 3.6v fb1 = v fb3 = 1.5v fb2 = i fb3 = 0v temperature (c) C50 uvlo voltage (v) 2.202.15 2.10 2.05 2.00 25 07 5 3587 g03 125 100 C25 50 temperature (c) C50 regulation voltage (v) v ifb3 , v vfb3 regulation voltage (v) 1.2401.230 1.220 1.210 1.200 0.8250.813 0.800 0.788 0.775 25 07 5 3587 g04 125 100 C25 50 v fb3 v ifb3 fb1 v vin = 3.6v r fb1 = r vfb3 = 1m r ifb3 = 8.06k i vout1 = 50ma i vout3 = 20ma temperature (c) C50 fb2 regulation voltage (mv) 1510 50 C5 C10 25 07 5 3587 g05 125 100 C25 50 v vin = 3.6v r fb2 = 1m i vneg = 100ma temperature (c) C50 bias current (a) i fb3 bias current (a) 14.5014.25 14.00 13.50 13.7513.25 13.00 106104 102 98 10096 94 25 07 5 3587 g06 125 100 C25 50 v vin = 3.6v r fb1 = r vfb3 =1m r ifb3 =8.06k i vout1 = 50ma i vout3 = 20ma i vfb3 i fb1 i ifb3 temperature (c) C50 fb2 bias current (a) C7.75C7.85 C7.95 C8.15 C8.05C8.25 25 07 5 3587 g07 125 100 C25 50 v vin = 3.6v r fb2 =1m i vneg = 100ma downloaded from: http:///
lt3587 5 3587fc typical performance characteristics switching frequency vs temperature switches v cesat vs current switches current limit vs temperature speci? cations are at t a = 25c unless otherwise noted. sw1 and sw2 current limit vs en/ss1 voltage temperature (c) C50 frequency (mhz) 1.201.10 1.00 0.90 0.80 25 07 5 3587 g08 125 100 C25 50 v vin = 3.6v sw current (a) 0 v cesat (v) 0.50.4 0.3 0.2 0.1 0 0.4 0.2 0.8 3587 g09 1.2 1 0.6 v vin = 3.6v sw1 sw2 sw3 temperature (c) C50 current limit (a) 1.21.0 0.4 0.6 0.80.2 0 25 07 5 3587 g10 125 100 C25 50 v vin = 3.6v duty cycle = 60% sw1 sw2 sw3 duty cycle (%) 0 current limit (a) 2.52.0 1.0 1.50.5 0 60 50 40 20 30 80 3587 g11 100 90 10 70 v vin = 3.6v sw1 sw2 sw3 en/ss1 voltage (v) 0.5 current limit (a) 1.61.2 0.4 0.8 0 1.7 1.5 1.3 0.9 1.1 2.1 3587 g12 2.5 2.3 0.7 1.9 v vin = 3.6v duty cycle = 60% sw1 sw2 switches current limit vs duty cycle sw3 current limit vs en/ss3 voltage en/ss3 voltage (v) 0.5 current limit (a) 0.50.4 0.2 0.1 0.3 0 1.7 1.5 1.3 0.9 1.1 2.1 3587 g13 2.5 2.3 0.7 1.9 v vin = 3.6v sw3 en/ss1, en/ss3 pull-up current in shutdown vs temperature temperature (c) C50 pull-up current (a) 1.501.25 0.75 1.000.50 25 07 5 3587 g16 125 100 C25 50 v vin = 3.6v en/ss1 = en/ss3 = 0v output disconnects on resistance vs temperature (r disc1 , r disc3 ) output disconnects current limit vs temperature temperature (c) C50 on resistance () 1412 6 8 10 42 25 07 5 3587 g14 125 100 C25 50 v vin = 3.6v i vout1 = 50ma i vout3 = 20ma r disc1 r disc3 temperature (c) C50 output disconnects current limit (ma) 200.0167.5 102.5 135.0 70 25 07 5 3587 g15 125 100 C25 50 v vin = 3.6v v vout1 = v vout3 = 15v i vout1 i vout3 downloaded from: http:///
lt3587 6 3587fc v out3 (pin 1): boost3 output pin. this pin is the drain of an output disconnect pmos transistor. cap3 (pin 2): boost3 output capacitor pin. this pin is the source of an output pmos disconnect. connect a capacitor from this pin to ground. sw3 (pin 3): boost3 switch pin. connect an inductor from this pin to v in . minimize trace area at this pin to minimize emi.gnd (pin 4, 7, 8, 12): ground pins. flt (pin 5): fault pin. this pin is a bidirectional open- drain pull-down pin. this pin pulls low when any of the enabled outputs fall out of regulation for more than 16ms. each output is ignored during start-up until its respective enable/soft-start pin allows for full inductor current. this pin can also be externally forced low to disable all the supply outputs. once this pin goes low (either due to an out of regulation condition or externally forced low), the pin latches low until the inputs to en/ss1 and en/ss3 are set low or the input supply pin is recycled. pull up this pin to v in with a 200k resistor when not used. fb2 (pin 6): inverter output voltage feedback pin. con- nect a resistor r fb2 from this pin to the inverter output (v neg ) such that: r fb2 = |v neg |/8a note that fb2 pin voltage is about 0v when in regulation. there is an internal 153k resistor from the fb2 pin to the internal reference. sw2 (pin 9): inverter switch pin. connect an inductor between this pin and v in , as well as the ? ying capacitor from this pin to the anode of the lnverter ground return diode. minimize trace area at this pin to minimize emi. nc (pin 10): no connect pin. leave open or connect to ground.sw1 (pin 11): boost1 switch pin. connect an inductor from this pin to v in . minimize trace area at this pin to minimize emi.cap1 (pin 13): boost1 output capacitor pin. this pin is the source of an output pmos disconnect. connect a capacitor from this pin to ground. en/ss1, en/ss3 shutdown threshold vs temperature cap3 overvoltage clamp vs temperature typical performance characteristics speci? cations are at t a = 25c unless otherwise noted. pin functions temperature (c) C50 shutdown threshold voltage (v) 0.450.40 0.25 0.350.30 0.20 25 07 5 3587 g17 125 100 C25 50 v vin = 3.6v temperature (c) C50 cap3 ov clamp voltage (v) 3130 29 28 27 25 07 5 3587 g18 125 100 C25 50 v vin = 3.6v downloaded from: http:///
lt3587 7 3587fc pin functions v out1 (pin 14): boost1 output pin. this pin is the drain of an output disconnect pmos transistor. fb1 (pin 15): boost1 output voltage feedback pin. con- nect a resistor r fb1 from this pin to v out1 (or cap1) such that: r fb1 = ((v vout1 /1.22v) C 1) ? 88.5k there is an internal 88.5k resistor from the fb1 pin to ground. en/ss1 (pin 16): boost1/inverter shutdown and soft-start pin. boost1 and inverter are enabled when the voltage on this pin is greater than 2.5v. they are disabled when the voltage is below 0.2v. an internal 1a current source in conjunction with an external capacitor can be used to ramp this pin and provide soft-start. v in (pin 17): input supply pin. must be locally bypassed with an x5r or x7r type ceramic capacitor. en/ss3 (pin 18): boost3 shutdown and soft-start pin. boost3 is enabled when the voltage on this pin is greater than 2v. it is disabled when the voltage is below 0.2v. an internal 1a current source in conjunction with an exter- nal capacitor can be used to ramp this pin and provide soft-start. i fb3 (pin 19): boost3 output current programming pin. connect a resistor r ifb3 from this pin to ground such that: r ifb3 = 200 ? (0.8v/i vout3 ) if boost3 output is con? gured as a voltage regulator, r ifb3 can be optionally used to limit the maximum output current to i limit : r ifb3 = 200 ? (0.8v/i limit ) note: tie i fb3 to gnd when no current limit is desired. v fb3 (pin 20): boost3 output voltage feedback pin. con- nect a resistor r vfb3 from this pin to v out3 (or cap3) such that: r vfb3 = ((v vout3 /0.8v) C 1) ? 56.3k there is an internal 56.3k resistor from the v fb3 pin to ground. in the current regulator con? guration, r vfb3 can be optionally used to limit the maximum output voltage to v clamp , such that: r vfb3 = ((v clamp /0.8v) C 1) ? 56.3k note: when no voltage clamp is desired in the current regulator con? guration, tie v fb3 to gnd. exposed pad (pin 21): ground pin. connect to pcb ground plane. ground plane connection through multiple vias under the package is recommended for optimum electrical and thermal performance. downloaded from: http:///
lt3587 8 3587fc block diagram figure 1. block diagram 3587 f01 C + ? + ? + ? + ? + v c1 v c2 v c3 filter and 16ms delay C + C + r q s disconnect control ramp generator sequencing r qq 1 s r q s ? + ramp generator r q s c5c6 v out3 v out1 v fb3 fb1 en/ss1 fb2 gnd r vfb3 r fb1 r fb2 en/ss3 v in 1 a a5 a8 v ref 0.8v flt 56.3k 88.5k soft- start 200mv v c3 a6 q3 ramp generator m2 m3 sw3cap3 v out3 v out1 i fb3 fltsw1 sw2 cap1 l4d s3 l1 c1 d s1 c4 r ifb3 100k c2 l2 l3 c7 v in v in v in v in v neg q2 a4 x2 a2 v c2 ptat bias bandgap and ldo oscillator en/ss1en/ss3 en/ss3 en/ss1 flt overvoltage protection disconnect control shdn3 v max a7 v ref 1.22v v in 1 a 200mv flt v in a1 soft- start 153k v c1 x1 x3 a3 c3 v neg shdn1 m1 d s2 downloaded from: http:///
lt3587 9 3587fc operation all three channels of the lt3587 use a constant frequency, current mode control scheme to provide voltage and/or current regulation at the output. operation can be best un- derstood by referring to the block diagram in figure 1. if en/ss1 is pulled higher than 200mv, the bandgap refer- ence, the start-up bias and the oscillator are turned on. at the start of each oscillator cycle, the sr latch x1 is set, which turns on the power switch q1. a voltage proportional to the switch current is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the pwm comparator a3. when this voltage exceeds the level at the negative input of a3, the sr latch x1 is reset, turning off the power switch q1. the level at the negative input of a3 is set by the error ampli? er a1, which is simply an ampli? ed version of the difference between the reference voltage of 1.22v and the feedback voltage. in this manner, the error ampli? er sets the correct peak switch current level to keep the output voltage in regulation. if the error ampli? er output increases, more current is delivered to the output; if it decreases, less current is delivered. the second channel is an inverting converter. this channel is also enabled through the en/ss1 pin. the basic opera- tion of this second channel is the same as the positive channel. the sr latch x2 is also set at the start of each oscillator cycle. the power switch q2 is turned on at the same time as q1. q2 turns off based on its own feedback loop, which consists of error ampli? er a2 and pwm comparator a4. the reference voltage of this negative channel is ground. voltage clamps (not shown) on the output of the error ampli? ers a1 and a2 enforce current limit on q1 and q2 respectively. similar to the ? rst channel, the third channel is also a positive boost regulator. if en/ss3 is pulled higher than 200mv, the bandgap reference, the start-up bias and the oscillators are also turned on. the sr latch x3 is set at the start of each oscillator cycle which turns on the power switch q3. q3 turns off based on its own feedback loop, which consists of error ampli? er a5 and pwm comparator a6. the level at the negative input of a6 is set by the error ampli? er a5, and is an ampli? ed version of the difference between the reference voltage of 0.8v and the maximum of the two feedback voltages at v fb3 and i fb3 . a separate comparator (not shown) sets the maximum current limit on q3. the i fb3 pin is pulled up internally with a current that is (1/200) times the load current out of the v out3 pin. therefore, an external resistor connected from this pin to ground generates a feedback voltage proportional to the v out3 output load current at the i fb3 pin. when the voltage at v fb3 is higher than the voltage at i fb3 , the third channel regulates to the feedback voltage at v fb3 , which in normal application is a divided down voltage from v out3 . in this state, the third channel behaves as a boost voltage regulator. on the other hand if the voltage at i fb3 is higher, the third channel regulates to the feedback voltage at i fb3 , which therefore regulates the v out3 output load current to a particular value. in this state, the third channel behaves as a boost current regulator. pmos m1 is used as an output disconnect pass transistor for the ? rst channel. m1 disconnects the load (v out1 ) from the input as long as the voltage between cap1 and v in is less than 2.5v (typical) and the voltage between cap1 and v out1 is less than 10v (typ). similarly, pmos m3 is used as an output disconnect pass transistor for the third channel. m3 disconnects the load (v out3 ) from the input when the third channel is in shutdown (en/ss3 voltage is lower than 200mv) and the voltage between cap3 and v out3 is less than 10v (typical). downloaded from: http:///
lt3587 10 3587fc inductor selectiona 15h inductor and a 10h inductor are recommended for the lt3587 boost1 channel and boost3 channel re- spectively. the inverting channel can use 15h or 22h inductors. although small size is the major concern for most applications, for high ef? ciency the inductors should have low core losses at 1mhz and low dcr (copper wire resistance). the inductor dcr should be on the order of half of the switch on resistance for its channel: 0.5 for boost1, 0.4 for the inverter and 1 for boost3. for robust applications, the inductors should have current ratings corresponding to their respective peak current during regulation. furthermore, with no soft-start, the inductor should also be able to withstand temporary high start-up currents of 1a, 1.1a and 480ma for the boost1, inverter and boost3 channels respectively (typ, refer to the typical performance characteristics curves). capacitor selection the small size of ceramic capacitors makes them suitable for lt3587 applications. x5r and x7r types of ceramic capacitors are recommended because they retain their capacitance over wider voltage and temperature ranges than other types such as y5v or z5u. a 1f input ca- pacitor is suf? cient for most lt3587 applications. the output capacitors required for stability depend on the application. for most applications, the output capacitor values required are: 10f for the boost1 channel, 22f for the inverter channel and 2.2f for the boost3 chan- nel. the inverter requires a 2.2f ? ying capacitor. note that this ? ying capacitor needs a voltage rating of at least v in + |v neg |. inrush currentwhen a supply voltage is abruptly applied to the v in pin, the voltage difference between the v in pin and the cap pins generates inrush current. for the case of the boost1 channel, the inrush current ? ows from the input through the inductor l1 and the schottky d s1 to charge the boost1 output capacitor c1. similarly for the boost3 channel, the inrush current ? ows from the input through the inductor l4 and the schottky d s3 to charge the output capacitor c4. applications information for the inverting channel, the inrush current ? ows from the input through inductor l2, charging the ? ying capacitor c2 and returning through the schottky diode d s2 . the selection of inductor and capacitor values should ensure that the peak inrush current is below the rated momentary maximum current of the schottky diodes. the peak inrush current can be estimated as follows: i p = (v vin 0.6) ? e 1 ? tan 1 ( ? ) lc ?= 4l r 2 c 1 where l is the inductance, c is the capacitance and r is the total series resistance in the inrush current path, which includes the resistance of the inductor and the schottky diode. note that in this equation, we model the schottky as having a ? xed 0.6v drop. table 1 gives inrush peak currents for some component selections. note that inrush current is not a concern if the input voltage rises slowly. table 1. inrush peak current v vin (v) r ( ) l (h) c (f) i p (a) 5 0.68 15 10 2.48 5 0.68 22 2.2 1.19 5 0.68 10 2.2 1.64 3.6 0.745 15 10 1.64 3.6 0.745 22 2.2 0.80 3.6 0.745 10 2.2 1.10 schottky diode selectionfor any of the external diode (d s1 , d s2 and d s3 ) selec- tions, besides having suf? ciently high reverse breakdown voltage to withstand the output voltage, both forward volt- age drop and diode capacitance need to be considered. schottky diodes rated for higher current usually have lower forward voltage drops and larger capacitance. although lower forward voltage drop is good for ef? ciency, a large downloaded from: http:///
lt3587 11 3587fc figure 3. boost3 con? gured as a voltage regulator and as a current regulator capacitance will slow down the switching waveform, which can cause signi? cant switching losses at 1mhz switch- ing frequency. some recommended schottky diodes are listed in table 2. table 2. recommended schottky diodes part number forward current (ma) forward voltage drop (v) diode capaci- tance (pf at 10v) manufacturer rsx051va-30 1000 0.35 30 rohm www.rohm.com pmeg401ocej 500 0.49 25 nxp/phillips www.nxp.com pmeg2005eb 500 0.43 8 ir05h40csptr 500 0.48 39 vishay www.vishay.com b0540ws 500 0.48 20 diodes inc. www.diodes.com zlls400 520 0.53 17 zetex www.zetex.com smaller footprint inverter topology in certain applications with higher tolerance of current ripple at the output of the inverter, the inductor l3 can be replaced with a schottky diode. since the schottky diode footprint is usually smaller than the inductor footprint, this alternate topology is recommended if a smaller overall solution is a must. note that this topology is only viable if the absolute value of the inverter output is greater than v in . this schottky diode is con? gured with the anode connected to the output of the inverter and the cathode to the output end of the ? ying capacitor c2 as shown in figure 2. applications information the same constraints as the other schottky diodes ap-ply for selecting d3. therefore, the same recommended schottky diodes in table 2 can be used for d3. boost3 overcurrent and overvoltage protection as brie? y discussed in the operation section, the regula- tion loop of boost3 uses the maximum of the two voltages at v fb3 and i fb3 as feedback information to set the peak current of its power switch q3. this allows for the boost3 loop to be con? gured as either a boost voltage regulator or a boost current regulator (figure 3). furthermore, this architecture also allows for a programmable current limit on voltage regulation or voltage limit on current regulation. figure 2. inverter con? gured with a schottky diode in place of the output inductor 3587 f02 sw2 fb2 lt3587 r fb1 1m v vin 2.5v to 4.5v c2 2.2f l2 15h d3 inverter output C8v, 100ma ds2 c722f 3587 f03 lt3587 boost3 voltage regulator v in v vin sw3 en/ss3 i fb3 cap3 v out3 v fb3 r vfb3 voltage regulation feedback resistor r ifb3 optionalprogrammable current limit resistor lt3587 boost3 current regulator v in v vin sw3 en/ss3 i fb3 cap3 v out3 v fb3 r vfb3 optional programmable voltage limit resistor r ifb3 current regulation feedback resistor when con? gured as a boost voltage regulator, a feedback resistor from the output pin v out3 to the v fb3 pin sets the voltage level at v out3 at a ? xed level. in this case, the i fb3 pin can either be grounded if no current limiting is desired or connected to ground with a resistor such that: i limit = 200 ? (0.8v/r ifb3 ) where i limit is the desired output current limit value. recall that the pull-up current on the i fb3 pin is controlled to be typically 1/200 of the output load current at the v out3 pin. in this case, when the load current is less than i limit , the boost3 loop regulates the voltage at the v fb3 pin to 0.8v. when there is an increase in load current beyond i limit , the voltage at v fb3 starts to drop and the voltage at i fb3 rises above 0.8v. the boost3 loop then regulates the voltage at the i fb3 pin to 0.8v, limiting the output downloaded from: http:///
lt3587 12 3587fc applications information current at v out3 to i limit . figure 4 compares the transient responses with and without current limit when a current overload occurs. figure 4. boost3 waveform in an output current overload event with and without output current limit lower than 29v is obtained by connecting a resistor from the v out3 pin to the v fb3 pin such that: r fb3 = ((v clamp /0.8v) C 1) ? 56.3k where v clamp is the desired output voltage clamp level. in this case, when the voltage level is less than v clamp , the boost3 loop regulates the voltage at the i fb3 pin to 0.8v. when the output load fails open-circuit or is disconnected, the voltage at i fb3 drops to re? ect the lower output current and the voltage at v fb3 starts to rise. when the voltage at v out3 rises to v clamp , the boost3 loop then regulates the voltage at the v fb3 pin to 0.8v, limiting the voltage level at v out3 to v clamp . figure 5 contrasts the transient responses with and without programmed v clamp when the output load is disconnected. figure 5. boost3 output open-circuit waveform with and without programmed output voltage clamp 3587 f04a v vin = 3.6v without current limit: i fb3 connected to gndv out3 stays at 15v, output current increases from 20ma to 40ma i l4 200ma/div v vout3 5v/div i vout3 13ma/div 200s/div 15v 20ma load step 3587 f04b v vin = 3.6v with 20ma current limit: r ifb3 = 8.06k output current stays at 20ma,v out3 drops from 15v to 7.5v i l4 200ma/div v vout3 5v/div i vout3 13ma/div 200s/div 15v 20ma load step 3587 f05a v vin = 3.6v without programmed output voltageclamp: v fb3 connected to gnd i l4 200ma/div v vout3 10v/div 200s/div 20v output loaddisconnected 3587 f05b v vin = 3.6v with programmed output voltage clamp at 24v i l4 200ma/div v vout3 10v/div 200s/div 20v output loaddisconnected the lt3587 cap3 pin has an internal overvoltage protec- tion. when the voltage at the cap3 pin is driven above 29v (typ), the boost3 loop is disabled and the sw3 pin stops switching. when con? gured as a boost current regulator, a feedback resistor from the i fb3 pin to ground sets the output cur- rent at v out3 at a ? xed level. in this case, if the v fb3 pin is grounded then the overvoltage protection defaults to the open-circuit clamp voltage level of 29v. a voltage clamp downloaded from: http:///
lt3587 13 3587fc applications information setting the output voltages and the boost3 output current the lt3587 has a trimmed internal feedback resistor. a 1m feedback resistor from each output pin to its corresponding feedback pin sets the outputs to 15v for boost1, C8v for the inverter and 15v for boost3. note that only one resistor is needed to set the output voltage for each channel. set the output voltages according to the following formulas: r fb1 = ((v vout1 /1.22v) C 1) ? 88.5k r fb2 = |v neg |/8a r vfb3 = ((v vout3 /0.8v) C 1) ? 56.3k as described in previous sections, boost3 can be con? gured as a boost current regulator. when con? gured as such, set the output current according to the following formula: r ifb3 = 200 ? (0.8v/i vout3 ) in order to maintain accuracy, use high precision resistors when setting any of the channels output voltage and/or the boost3 output current (1% is recommended). soft-start the lt3587 has two soft-start control pins: en/ss1 and en/ss3. the en/ss1 pin controls the soft-start for both the boost1 and the inverter, while the en/ss3 pin controls the soft-start for the boost3. each of these soft-start pins is pulled up internally with a 1a current source. connecting a capacitor from the en/ss1 pin to ground programs a soft-start ramp for the boost1 and the inverter channels. use an open-drain transistor to pull this pin low to shut down both the boost1 and the inverter. turning off this transistor allows the 1a pull-up current to charge the soft-start capacitor. when the voltage at the en/ss1 pins goes above 200mv, the regulation loops for boost1 and the inverter are enabled. the v c1 node voltage follows the en/ss1 voltage as it continues to ramp up to ensure slow start-up on the boost1 channel. the v c2 node follows the ramp voltage minus 0.7v. this ensures that the inverter starts up after the boost1, but still has a slow ramping output to avoid large start-up currents. the boost1 and the inverter regulation loops are free running with full inductor current when the voltage at the en/ss1 pin is above 2.5v. connecting a capacitor from the en/ss3 pin to ground sets up a soft-start ramp for the boost3 channel. as the 1a current charges up the capacitor, the boost3 regula- tion loop is enabled when the en/ss3 pin voltage goes above 200mv. the v c3 node voltage follows the en/ss3 voltage as it ramps up ensuring slow start-up on the boost3 channel. when the voltage at the en/ss3 pin is above 2v, the boost3 regulation loop is free running with full inductor current. start sequencing the lt3587 also has internal sequencing circuitry that inhibits the inverter channel from operating until the feed- back voltage of the boost1 voltage (at the fb1 pin) reaches about 1.1v (87% of the ? nal voltage). this ensures that the boost1 output voltage is near regulation before any negative voltage is generated at the inverter output. figure 6 contrasts the start-up sequencing without any soft-start capacitor, and with a 10nf soft-start capacitor. figure 6. v en/ss1 , v out1 , v neg , i vin with no soft-start capacitor, and with a 10nf soft-start capacitor 3587 f06a i vin 500ma/div v vout1 10v/div v neg 10v/div v en/ss1 2v/div 400s/div 0v 0v 0v 0ma 3587 f06b i vin 500ma/div v vout1 10v/div v neg 10v/div v en/ss1 2v/div 4ms/div 0ma 0v 0v downloaded from: http:///
lt3587 14 3587fc applications information output disconnectboth the boost1 and the boost3 channels have an output disconnect between their respective cap pin and v out pin. this disconnect feature prevents a dc path from v in to v out . for boost1, this output disconnect feature is implemented using a pmos (m1) as shown in the block diagram in figure 1. when turned on, m1 is driven hard in the linear region to reduce power dissipation when delivering cur- rent between the cap1 pin and the v out1 pin. m1 stays on as long as the voltage difference between cap1 and v in is greater than 2.5v. this allows for the positive bias to stay high for as long as possible as the negative bias discharges during turn off. the disconnect transistor m1 is current limited to provide a maximum output current of 155ma (typ). however, there is also a protection circuit for m1 that limits the voltage drop across cap1 and v out1 to about 10v. when the voltage at cap1 is greater than 10v, in an overload or a short-circuit event, m1 current is limited to 155ma until the voltage across cap1 to v out1 grows to about 10v. then m1 is turned on hard without any current limit to allow for the voltage on cap1 to discharge as fast as possible. when the voltage across cap1 and v out1 reduces to less than 10v, the output current is then again limited to 155ma. figure 7 shows the output voltage and current during an overload event with v cap1 initially at 15v. figure 7. v cap1 ,v vout1 , i vout1 and i l1 during a short-circuit event figure 8. v cap3 , v vout3 , i vout3 and i l4 during a short-circuit condition with and without programmed 20ma current limit 3587 f07 i l1 500ma/div v cap1 10v/div v vout1 10v/div i vout1 500ma/div 40s/div v vin = 3.6v c1 = 4.7f 0ma 15v 15v 3587 f08a i l4 500ma/div v cap3 10v/div v vout3 10v/div i vout3 500ma/div 40s/div 0ma 24v 3587 f08b i l4 500ma/div v cap3 10v/div v vout3 10v/div i vout3 500ma/div 40s/div 24v 0ma v vin = 3.6v c4 = 1f the output disconnect feature on boost3 is implemented similarly using m3. however, in this case m3 is only turned off when the en/ss3 pin voltage is less than 200mv and the boost3 regulation loop is disabled. the disconnect transistor m3 is also current limited, pro- viding a maximum output current at v out3 of 110ma (typ). m3 also has a similar protection circuit as m1 that limits the voltage drop across cap3 and v out3 to about 10v. figure 8 shows the output voltage and current during an overload event with v cap3 initially at 24v. choosing a feedback node boost1 feedback resistor, r fb1 , may be connected to the v out1 pin or the cap1 pin (see figure 9). similarly for boost3 in a boost voltage regulator con? guration, the feedback resistor, r vfb3 , may be connected to the v out3 pin or the cap3 pin. regulating the v out1 and v out3 pins eliminates the output offset resulting from the voltage drop across the output disconnect pmos transistors. downloaded from: http:///
lt3587 15 3587fc applications information however, in the case of a short-circuit fault at the v out pins, the lt3587 will switch continuously because the fb1 or the v fb3 pin is low. while operating in this open-loop condition, the rising voltage at the cap pins is limited only by the protection circuit of their respective output disconnects. at the worst case, the cap pin rises to 10v above the corresponding v out pin. so in the case of short- circuit fault to ground, the voltage on the cap pins may reach 10v. when the short-circuit condition is removed, the v out pins rise up to the voltage on the cap pins, potentially exceeding the programmed output voltage until the capacitor voltages fall back into regulation. while this is harmless to the lt3587, this should be considered in the context of the external circuitry if short-circuit events are expected. regulating the cap pins ensures that the voltage on the v out pins never exceeds the set output voltage after a short-circuit event. however, this setup does not com- pensate for the voltage drop across the output disconnect, resulting in an output voltage that is slightly lower than the voltage set by the feedback resistor. this voltage drop is equal to the product of the output current and the on resistance of the pmos disconnect transistor. this drop can be accounted for when using the cap pin as the feedback node by setting the output voltage according to the following formula: figure 10. waveforms during fault detection of a short-circuit event r fb1 = v vout1 + i vout1 ?r disc1 1.22v 13.8 a r fb3 = v vout3 + i vout3 ?r disc3 0.8v 14.3 a fault detection and indicator the lt3587 features fault detection on all its outputs and a fault indicator pin ( flt ). the fault detection circuitry is enabled only when at least one of the channels has com-pleted the soft-start process and is free running with full inductor current. once the fault detection is enabled, the fault pin pulls low when any of the feedback voltages (v fb1 , v fb2 or max(v vfb3 ,v ifb3 )) fall below their regulation value for more than 16ms. one particularly important case is an overload or short- circuit condition on any of the channel outputs. in this case, if the corresponding loop is unable to bring the output back into regulation within 16ms, a fault is detected and the fault pin is pulled low. note that the fault condition is latched. once the fault pin is pulled low, all the three channels are disabled. in order to enable any of the channels again, reset the part by shut- ting it down and then turning it on again. this is done by ? rst forcing both the en/ss1 and en/ss3 pins low below 200mv and then either letting them go high again in a soft-start process or forcing them high immediately if no soft-start is desired. figure 10 shows the waveforms when a short-circuit condition occurs at boost1 for more than 16ms as well as the subsequent resetting of the part. 3587 f10 enss1/enss3 5v/div v neg 10v/div v vout3 20v/div v vout1 10v/div v flt 5v/div 100ms/div part reset short at v out1 figure 9. feedback connection using the v out and cap pins 3587 f09 v out3 cap3v fb3 i fb3 sw2 dn fb2 gnd cap1 fb1 v out1 lt3587 flt b1 en/ss b3 en/ss sw3 sw1 v in v out3 cap3v fb3 i fb3 sw2 dn fb2 gnd cap1 fb1 v out1 lt3587 flt b1 en/ss b3 en/ss sw3 sw1 v in r vfb3 r fb1 r vfb3 r fb1 downloaded from: http:///
lt3587 16 3587fc figure 12. dimming using a dac and a resistor applications information besides acting as a fault output indicator, the fault pin is also an input pin. if this pin is externally forced low below 400mv, the lt3587 behaves as if a fault event has been detected and all the channels turn off. in order to turn the part back on, remove the external voltage that forces the pin low and reset the part. figure 11 shows the waveforms when the fault pin is externally forced low and the subsequent resetting of the part. since the programmed v out3 current is proportional to the current through r ifb3 , the led current can be adjusted according to the following formula: i vout3 = (0.8v C v dac-out ) ? 200/r ifb3 a higher dac output voltage level results in lower led current and hence lower overall brightness. conversely, a lower dac output voltage results in higher led current and higher brightness. note that the dac output impedance should be low enough to be able to sink approximately 1/200 of the desired maximum led current without any appreciable error for accurate dimming control. note also that the maximum output current is limited by the output disconnect current limit to 110ma (typ). pwm dimming changing the forward current ? owing in the leds not only changes the brightness intensity of the leds, it also changes the color. the chromaticity of the leds changes with the change in forward current. many applications cannot tolerate any shift in the color of the leds. control- ling the intensity of the leds with a direct pwm signal allows dimming of the leds without changing the color. in addition, direct pwm dimming offers a wider dimming range to the user. 10 h 3587 f12 v out3 cap3 i fb3 lt3587 r ifb3 8.06k en/ss3 sw3 v in led driver 1 f v vin 2.5v to 5v v dac-out dac ltc2630 figure 11. waveforms when the fault pin is externally forced low 3587 f11 enss1/enss3 5v/div v neg 10v/div v vout3 20v/div v vout1 10v/div v flt 5v/div 100ms/div part reset flt forced low dimming control for boost3 current regulator as an led driver as shown on the front page application and the block dia- gram, one of the most common applications for the boost3 channel when con? gured as a boost current regulator is a backlight led driver. in an led driver application, there are two different ways to implement a dimming control of the led string. the led current can be adjusted either by using a digital to analog converter (dac) with a resistor r ifb3 or by using a pwm signal. using a dac and a resistorfor some applications, the preferred method of brightness control is using a dac and a resistor. the boost3 con? gura- tion for using this method is shown in figure 12. downloaded from: http:///
lt3587 17 3587fc applications information figure 14. pwm dimming waveforms dimming the leds via a pwm signal essentially involves turning the leds on and off at the pwm frequency. the typical human eye has a sensitivity limit of ~60hz. by increasing the pwm frequency to ~80hz or higher, the eye will interpret that the pulsed light source is continuously on. additionally, by modulating the duty cycle (amount of on-time), intensity of the leds is controlled. the color of the leds remains unchanged in this scheme since the led current is either zero or a constant value. figure 13 shows a partial application showing an led driver for six white leds. if the voltage at the cap3 pin is higher than 10v when the leds are on, direct pwm dim- ming method requires an external nmos. this external nmos is tied between the cathode of the lowest led in the string and ground as shown in figure 13. a si1304 logic-level mosfet can be used since its source is connected to ground, and it is able to withstand the open-circuit voltage at the v out3 pin across its drain and source. the pwm signal must be applied to the en/ss3 pin of the lt3587 and the gate of the nmos. the pwm signal should traverse between 0v to 2.5v, to ensure proper turn on and off of the boost3 regulation loop and the nmos transistor mn1. when the pwm signal goes high, the leds are connected to ground and a current of i vout3 = 160v/r ifb3 ? ows through the leds. when the pwm signal goes low, the leds are disconnected and turned off. the output disconnect feature and the external nmos ensure that the leds quickly turn off without discharging the output capacitor. this allows the leds to turn on faster. figure 14 shows the pwm dimming waveforms for the circuit in figure 13. figure 13. six white leds driver with pwm dimming 10 h 3587 f13 v out3 cap3 i fb3 lt3587 r ifb3 8.06k en/ss3 sw3 v in led driver 20ma 1 f v vin 2.5v to 5v pwm freq 2.5v 0v mn1si1304bdl 3587 f14 enss3 5v/div i l4 200ma/div i vout3 13ma/div 2ms/div v vin = 3.6v 6 leds 0ma 0ma 0v downloaded from: http:///
lt3587 18 3587fc figure 16. dimming range comparison of three pwm frequencies the time it takes for the led current to reach its pro-grammed value sets the achievable dimming range for a given pwm frequency. figure 15 shows the average current variation over duty cycle for a 100hz pwm frequency with the circuit in figure 13. notice that at lower end of the duty cycle, the linear rela- tion between the average led current and the pwm duty cycle is no longer preserved. this indicates that the loop requires a ? xed amount of time to reach its ? nal current. when the duty cycle is reduced such that the amount of on time is in the order of or less than this settling time, the loop no longer has the time to regulate to its ? nal current before it is turned off again and the initial current before settling is a larger proportion of the average current. depending on how much linearity on the average led current is required, the minimum led on time is chosen based on the graphs in figure 15. for example, for ap- proximately 10% deviation from linearity at the lower duty cycle, the minimum on time of the led current is approximately 320s for a 3.6v input voltage. the achievable dimming range for this application with a 100hz pwm frequency can be determined using the following method. applications information example: f = 100hz t period = 1/f = 0.01s, t min-on = 320s dim range = t period /t min-on = 0.01s/320s 30:1 min duty cycle = (t min-on /t period ) ? 100 = 3.2% duty cycle range = 100% 3.2% at 100hz the calculations show that for a 100hz signal the dimming range is 30 to 1. in addition, the minimum pwm duty cycle of 3.2% ensures that the led current varies linearly with duty cycle to within 10%. figure 16 shows the dimming range achievable for three different frequencies with a minimum on time of 320s. the dimming range can be further extended by combin- ing this pwm method with the dac and resistor method discussed previously. in this manner both analog dimming and pwm dimming extend the dimming range for a given application. the color of the leds no longer remains constant because the forward current of the led changes with the output voltage of the dac. for the six led ap- plication described above, the leds can be dimmed ? rst by modulating the duty cycle of the pwm signal with the dac output at 0v. once the minimum duty cycle is reached, the value of the dac output voltage can be increased to further dim the leds. the use of both techniques together allows the average led current for the six led application to be varied from 20ma down to less than 1a. pwm dimming range 3587 f16 1 10 100 1khz 300hz 100hz figure 15. average led current variation with pwm duty cycle at 100hz pwm frequency duty cycle (%) average current (ma) 3587 f15 100 0.1 1 10 0.01 1 10 100 ideal measured downloaded from: http:///
lt3587 19 3587fc applications information lower input voltage applications the lt3587 can be used in lower input voltage applica- tions. the v in supply voltage to the lt3587 must be 2.5v to 6v. however, the inductors can be run off a lower voltage. this allows the outputs to be powered off two alkaline cells. most portable devices and systems have a 3.3v logic supply voltage which can be used to power figure 17. 2 aa cells providing ccd positive and negative supply and a three white backlight led driver l1 15 h l4 10 h 3587 f17 i fb3 en/ss3 en/ss1 flt sw2 gnd fb2 cap1 fb1 v out1 lt3587 v fb3 v out3 cap3 sw3 sw1 c1 4.7 f r fb1 787k ccd positive 12v, 10ma 2aa cells 2v to 3.2v c2 2.2 f l2 15 h l3 15 h r fb2 1m ccd negative C8v, 20ma led driver 20ma up to 12v 2aa cells2v to 3.2v c710 f d s2 v in d s3 c41 f r vfb3 787k (optional) d s1 r ifb3 8.06k c1: murata grm21br61e475ka12l c2: murata grm188r61c225ke15d c4: murata grm188r61e105ka12b c6: murata grm155r61a105ke15d c7: murata grm21br71a106ke51l c fb1 : murata grm1555c1h3r3bz01d c fb2 : murata grm1555c1h6r3bz01d l1, l2, l3: sumida cdrh2d18/hp-150nl4: toko 1071as-100m d s1 , d s2 , d s3 : nxp pmeg2005eb c61 f 3.3v c fb1 3.3pf c fb2 6.8pf the lt3587. the outputs can be driven straight from the battery, resulting in higher ef? ciency. figure 17 shows a typical digital still camera application with ccd positive and negative supply as well as an led driver powered by two aa cells. the battery is connected to the input inductors and the chip is powered with a 3.3v logic supply voltage. downloaded from: http:///
lt3587 20 3587fc applications information figure 19. recommended component placement figure 18. high current paths board layout considerationas with all switching regulators, careful attention must be paid to the pcb board layout and component placement. to maximize ef? ciency, switch rise and fall times are made as short as possible. to prevent electromagnetic interfer- ence (emi) problems, proper layout of the high frequency switching path is essential. in order to minimize magnetic ? eld radiation, reduce the parasitic inductance by keeping the traces that conduct high switching currents short, wide and with minimal overall loop area. these are typically the traces associated with the switches. figure 18 outlines the critical paths. c6 c1 sw1 gnd v vin l1 q1 cap1 d s1 lt3587 c6 c4 sw3 gnd v vin l4 q3 cap3 d s3 lt3587 3587 f18 c6 c7 sw2 gnd v vin v neg l2 l3 q2 d s2 lt3587 c2 the voltage signals of the sw1, sw2 and sw3 pins have rise and fall times of a few ns. minimize the length and area of all traces connected to the sw1, sw2 and sw3 pins to reduce capacitive coupling between these fast nodes and other circuitry. in particular, keep all the traces of the feedback voltage pins (fb1, fb2, v fb3 and i fb3 ) away from the switching node. always use a ground plane under the switching regulator to minimize interplane coupling. finally, place as much of the output capacitors of each channel close to their respective cap pins. recommended component placement is shown in figure 19. 3587 f19 l4 l3 l2 c7 c2 u1 l1 c1 c4 c6 (opt) c6 (opt) c6 (opt) ds2 ds1 r fb1 c fb1 c5 c6 c3 r ifb3 r fb2 c fb2 v neg v in cap3 v in v out3 v out1 cap1 v in ds3 downloaded from: http:///
lt3587 21 3587fc typical applications li-ion powered supply for ccd imager and five white backlight leds l1 15 h l4 10 h 3587 ta02 i fb3 en/ss3 en/ss1 flt sw2 gnd fb2 cap1 fb1 v out1 lt3587 v fb3 v out3 cap3 sw3 v in sw1 c61 f c1 10 f c fb1 2.7 p f r fb1 1m ccd positive 15v, 50ma v vin 2.5v to 6v c2 2.2 f l2 15 h l3 15 h r fb2 1m ccd negative C8v, 100ma led driver 20ma up to 24v v vin 2.5v to 6v c722 f d s2 d s3 c42.2 f r vfb3 1.65m (optional) d s1 r ifb3 8.06k c51 00n f c31 00n f c1: murata grm21br61c106ke15l c2: murata grm188r61c225ke15d c3, c5: murata grm033r60j104ke19d c4: murata grm21br71e225ka73l c6: murata grm155r61a105ke15d c7: taiyo yuden lmk212bj226mg-t c fb1 : murata grm1555c1h2r7bz01d c fb2 : murata grm1555c1h6r8bz01d l1, l2, l3: sumida cdrh2d18/hp-150nl4: toko 1071as-100m d s1 , d s2 , d s3 : ir ir05h40csptr c fb2 6.8 p f downloaded from: http:///
lt3587 22 3587fc typical applications driver for a ccd imager and an oled display panel with soft-start extending the high voltage range and the number of independently controlled regulated outputs l1 15 h l4 15 h 3587 ta04 v out3 cap3 v fb3 i fb3 sw2 gnd fb2 cap1 fb1 v out1 lt3587 flt en/ss1 en/ss3 sw3 sw1 v in c61 f supply 1: 18v, 50ma v vin 3v to 6v c2 2.2 f d3 r fb2 2.26m r ifb3 10.7k c4 2.2 f supply 3: 25v, 1ma to 10ma v vin 3v to 6v c722 f d s1 c1 10 f c fb1 2.2 p f r fb1 1.21m d s3 c5100nf c3 100nf d s2 d9 l2 22 h c1: murata grm31cr71e106ka12l c2, c8, c11: murata gcm21br71e225ka73l c3, c5: murata grm033r60j104ke19d c4: murata grm21br71e225ka73l c6: murata grm155r61a105ke15d c7: murata grm32er61e226ke15l c9, c12: murata grm31cr71h225ka55l c10, c13: murata grm21br71h105ka12l c fb1 : murata grm1555c1h2r2bz01d c fb2 : murata grm1555c1h2r7bz01d l1, l4: coilcraft lps4018-153 l2, l3: coilcraft lps4018-223 d s1 , d s2 , d s3 , d3, d4, d5, d6, d7, d9, d10: ir ir05h40csptr d8: diodes inc ddz9709t r vfb3 1.74m supply 2: C18v, 50ma c fb2 2.7 p f in out shdn adj lt3014 gnd r63.24m r7100k c131 f supply 5: 40v, 5ma c122.2 f c92.2 f d7 d5 d6 supply 1 d4 supply 2 c11 2.2f c8 2.2f in out shdn adj lt1964 gnd r5100k r61.21m c101 f d824v supply 4: C40v, 5ma d10 l1 15 h l4 10 h 3587 ta03 v out3 cap3 v fb3 i fb3 sw2 gnd fb2 cap1 fb1 v out1 lt3587 flt en/ss1 en/ss3 sw3 sw1 v in c61 f ccd positive 15v, 50ma v vin 2.5v to 6v c2 2.2 f d3 r fb2 1m ccd negative C8v, 100ma r ifb3 7.15k (optional) c4 1 f oled driver 16v, 20ma v vin 2.5v to 6v c722 f d s1 c1 4.7 f r fb1 1m d s3 c5100nf c fb2 6.8pf c3 100nf d s2 l2 15 h c1: taiyo yuden tmk212bj475kg-t c2: taiyo yuden emk107bj225ka-t c3, c5: taiyo yuden jmk063bj104kp-f c4: taiyo yuden gmk107bj105ka-t c6: taiyo yuden lmk105bj105kv-f c7: taiyo yuden lmk212bj226mg-t c fb1 : taiyo yuden emk105sk2r7jw-f c fb2 : taiyo yuden emk105sh6r8jw-f l1, l2: sumida cdrh2d18/hp-150nl4: toko 1071as-100m d s1 , d s2 , d s3 , d3: nxp pmeg2005eb r vfb3 1.07m c fb1 2.7pf downloaded from: http:///
lt3587 23 3587fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 1.65 0.05 note:1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1top mark (note 6) 0.40 0.10 bottom view?exposed pad 1.65 0.10 (4-sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 0.20 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 19 20 2 0.40 bsc 0.200 ref 2.10 0.05 3.50 0.05 (4 sides) 0.70 0.05 0.00 ? 0.05 (ud20) qfn 0306 rev a 0.20 0.05 0.40 bsc packageoutline package description ud package 20-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1720 rev a) downloaded from: http:///
lt3587 24 3587fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0109 rev c printed in usa related parts typical application part number description comments lt1944 dual output, boost/inverter, 350ma i sw , high ef? ciency boost-inverting dc/dc converter v in(min) = 1.2v, v in(max) = 15v, v out(max) = 34v, i q = 20, i sd < 1a, msop-10 package lt1945 dual output, boost/inverter, 350ma i sw , high ef? ciency boost-inverting dc/dc converter v in(min) = 1.2v, v in(max) = 15v, v out(max) = 34v, i q = 20, i sd < 1a, msop-10 package lt3463/lt3463a dual output, boost/inverter, 250ma i sw , constant off- time, high ef? ciency step-up dc/dc converter with integrated schottkys v in(min) = 2.3v, v in(max) = 15v, v out(max) = 40v, i q = 40a, i sd < 1a, 3 3 dfn-10 package lt3466/lt3466-1 dual constant current, 2mhz, high ef? ciency white led boost regulator with integrated schottky diode v in(min) = 2.7v, v in(max) = 24v, v out(max) = 40v, i q = 5ma, i sd < 16a, 3 3 dfn-10 package lt3471 dual output, boost/inverter, 1.3a i sw , 1.2mhz, high ef? ciency boost-inverting dc/dc converter v in(min) = 2.4v, v in(max) = 16v, v out(max) = 40v, i q = 2.5ma, i sd < 1a, 3 3 dfn-10 package lt3472/lt3472a dual output, boost/inverter, 400ma i sw , 1.2mhz, high ef? ciency boost-inverting dc/dc converter v in(min) = 2.2v, v in(max) = 16v, v out(max) = 34v i q = 2.8ma, i sd < 1a, 3 3 dfn-10 package lt3473/lt3473a 40v, 1a, 1.2mhz micropower low noise boost converter with output disconnect v in(min) = 2.2v, v in(max) = 16v, v out(max) = 36v, i q = 150a, i sd < 1a, 3 3 dfn-12 package lt3494/lt3494a 40v, 180ma/350ma micropower low noise boost converter with output disconnect v in(min) = 2.3v, v in(max) = 16v, v out(max) = 40v, i q = 65a, i sd < 1a, 3 2 dfn-8 package lt3497 dual 2.3mhz, full function led driver with integrated schottkys and 250:1 true color pwm dimming v in(min) = 2.5v, v in(max) = 10v, v out(max) = 32v, i q = 6ma, i sd < 12a, 2 3 dfn-10 package lt3580 40v, 2a, 2.5mhz boost/inverter dc/dc converter v in : 2.5v to 32v, v out(max) = 40v, i q = 1ma, i sd < 1a, msop-8e, 3mm 3mm dfn-8 packages general purpose high voltage supplies generator l1 15 h l4 10 h 3587 ta05 v out3 cap3 v fb3 i fb3 sw2 gnd fb2 cap1 fb1 v out1 lt3587 flt en/ss1 en/ss3 sw3 sw1 v in c61 f supply 1: 15v, 50ma v vin 2.5v to 6v c2 2.2 f r fb2 2m c fb2 2.2pf supply 2: C16v, 50ma r ifb3 6.34k c4 2.2 f supply 3: 25v supply with safety current limit at 25ma v vin 2.5v to 6v c722 f d s1 c1 10 f r fb1 1m d s3 c5100nf c3 100nf d s2 d s4 l2 22 h l3 22 h c1: murata grm31cr71e106ka12l c2: murata grm21br71e225ka73l c3, c5: murata grm033r60j104ke19d c4: murata grm21br71e225ka73l c6: murata grm155r61a105ke15d c7: murata grm32er61e226ke15l c fb1 : murata grm1555c1h2r7bz01d c fb2 : murata grm1555c1h2r2bz01d l1: coilcraft lps4018-153 l2, l3: coilcraft lps4018-223 l4: toko 1071as-100m d s1 , d s2 , d s3 , d s4 : ir ir05h40csptr r vfb3 1.74m c fb1 2.7pf downloaded from: http:///

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